TernaryCore

Multiplier-free ternary arithmetic for BitNet b1.58 inference on commodity FPGAs.

Weights constrained to {−1, 0, +1} turn matrix multiplication into conditional accumulation — add, subtract, skip. No multiplier, no DSP slices. We build the open hardware that runs it and distil the ternary-weight students that run on it.

What's here

• ternarycore-sst2-student — a 28-block ternary (W1.58A8) student distilled from Qwen3-0.6B for GLUE SST-2, with the packed 2-bit weights the accelerator consumes and a NumPy reference for element-by-element checking.

Hardware

The accelerator RTL, MicroBlaze firmware and host tooling live on GitHub at Ternarycore/ternarycore, released under CERN-OHL-S v2 and archived at 10.5281/zenodo.22837568. Silicon-validated on a commodity Artix-7 board, with whole-board energy measured by inline current sensing rather than estimated.

Interests

Ternary and low-bit quantization · quantization-aware training · knowledge distillation · reconfigurable computing · hardware–software co-design · energy measurement for edge inference